Module Number: 16
Title: Device Operation and Process
Delivered by: University of Glasgow
Module Credits: 15
- Pre-residential work: 3
- Post-residential work: 7
- Examination: 10
- Dr Scott Roy, University of Glasgow
- Dr Scott Roy
- Professor Asen Asenov
- Dr Jeremy Watling
- Professor Peter Ashburn, University
- Dr Darren Bagnall, University of
- Mr E Granville, Wolfson Microelectronics
- Mr P Tuohy, Motorola, East Kilbride
- Mr N Cameron, Intense Photonics,
The aim of this module is to introduce
delegates to the physics of devices and circuit operation and thereby
establish links between the process architecture, the corresponding
device structure and the resulting circuit performance.
On successful completion of this module
delegates will have obtained:
- a deep insight into the operation
of modern integrated devices.
- an appreciation of the link between
the device structure and the device characteristics.
- an understanding of how the device
layout and the fabrication recipe affect the device structure and
the device characteristics.
- new skills in the design of active
and passive IC components with specified characteristics.
- an understanding of the necessary
modification in the device technology accompanying the scaling of
the IC components.
- an appreciation of how device operation
influences circuit performance
- Pre-residential sessions: assignments
- Post-residential sessions: assignments
- Examination: (supervised) 50%
Background to the Module:
With the continuing scaling of semiconductor
devices to deep submicron dimensions, device operation becomes more
and more complex. The device characteristics become sensitive to small
variations in the pattern definition, doping profile and layer structure.
The separation of adjacent devices is also shrinking, thus increasing
the susceptibility to parasitic effects, leakage and cross talk. Process
and device modelling becomes crucial for understanding, designing and
optimising the devices and the corresponding technologies.
This module is designed for process
and device engineers involved in process design, optimisation and control,
and for circuit designers who wish to gain an in depth understanding
of device operation needed for advanced circuit design. It will be illustrated
with complete TCAD simulations of advanced CMOS, DRAM, bipolar and BiCMOS
technologies, including active devices, device isolation and interconnect.
The module will be split into MOS and bipolar sections. Starting in
each of the sections with device basics, the module will introduce advanced
aspects of device operation which will be linked to the device structure
and the process architecture.
Delegates will be expected to have
background knowledge at a level equivalent to a good honours degree
in a science or engineering discipline. It is highly desirable for delegates
to have successfully completed Module 1 'Introduction to IC Technology'
and thus have a knowledge of device physics, processing technologies
and process integration into whole processes.
Delivery & Assignments:
Delegates will be provided with a complete
set of lecture notes, instructions for the laboratory sessions and relevant
review articles for directed reading. Examples of simulation results
for advanced MOS and bipolar devices and complete CMOS, bipolar and
BiCMOS technologies will be available from restricted access pages on
the World Wide Web
- Pre-residential sessions:
- Advanced reading
- Written exercises
- Residential week (35 contact hours):
- Laboratory sessions
- Tutorials/Case studies
- Post-residential sessions:
- Advanced tutorial questions
- Written report (2000 to 4000
- Supervised examination (3 questions
out of 5, 2 hours)
- Lectures 25 hours
- Laboratory sessions 8 hours
- Case Studies/Tutorials 2 hours
||Energy bands in silicon;
Electron and holes, donors and acceptors; Fermi level, carrier statistics;
Generation and recombination; Drift current, mobility, resistivity,
velocity saturation; Diffusion current, Einstein relation; The basic
semiconductor equations p-n junction, built-in potential; Reverse
bias; Impact ionisation; Avalanche breakdown; Forward bias; Current-voltage
|Process & Device
|| The commercial imperative
for simulation; Keys to interpretation of simulation results - Calibration,
Physical understanding, Limitations and numerical accuracy;Basic principles
of simulation- Equations, discretization, meshing; Device Simulation
Approaches- 1D-2D-3D, Drift Diffusion, fluid & particle models; Hierarchical
simulation; Process simulation techniques- Diffusion, oxidation, implantation,
etch, Interfacing process & device simulation; Commercial simulation
Structure Physics. MOSFET Operation
||The ideal MOS structure;
Band diagram; Accumulation, flat band; Depletion, depletion approximation;
Inversion, strong inversion; Gate voltage equation; Threshold voltage;
Real MOS structure. Work function; Oxide and interface charge; MOSFET
operating principles; Current-voltage characteristic;s Gradual channel
approximation. Linear (triode) region; Pinch-off and current saturation;
Subthreshold region; Subthreshold slope.
|MOSFET Scaling. Short
|| The International Technology
Roadmap. Threshold roll-off. Charge-sharing model. Drain-induced Barrier
Lowering DIBL. Velocity saturation. Current-voltage characteristics.
Velocity overshoot. Channel length modulation. MOSFET breakdown. Hot
carrier degradation. MOSFET scaling. Constant field scaling. Generalised
scaling. Non-scaling effects.
|Gate Stack Engineering.
|| Threshold voltage definition
and tolerances. Uniform, high-low and arbitrary doping profiles. Channel
profile design. Effect of the workfunction. Gate material. Poly silicon
depletion effects. Ultra-thin gate oxides. Quantum confinement effects.
Quantum threshold voltage shift. Quantum degradation of transconductance.
Direct tunnelling and its limitations. High k gate dielectrics. Gate
resistance. Silicides. Intrinsic threshold voltage fluctuations.
Engineering. Punch-through control
to the source and drain. Trends of S/D structures. Technological aspects
- doping techniques and spacers. Trends of Xj and RS.
Series resistances in MOSFETs. Junction and overlap capacitances.
Advanced S/D S4D and RGSD. Threshold voltage vs. punch-through control.
Channel profile evolution. Selective, asymmetric and pocket doping.
Reverse short channel effects. Effective channel length.
|Process & Device
Simulation in MOSFET design
||Calibration for MOSFET
simulations. 1D Gate stack simulation- quantum effects. 2D idealised
device simulation - Input files/decks; Practical meshing considerations;
Efficiency vs. accuracy; Choice of mobility model; Data visualisation;
Design of Experiments. Non-equilibrium transport / submm devices -
Appropriate use of HD / MC techniques. Effective use of process simulation.
Problems amenable to simulation, and when not to bother.
|CMOS Well Engineering
||Requirements to wells.
Evolution. Single, double and triple wells. Downsizing the well. Impurity
concentration considerations. The impact of the gate selection on
the well design.SOI CMOS.
CMOS Isolation, Latch-up, Interconnects
CMOS Process Integration modules
| Evolution of the CMOS
isolation. LOCOS vs. Shallow Trench Isolation (STI). Field oxide threshold
and leakage. Narrow channel effects Latch-up in CMOS circuits. Remedy
to avoid latch-up. Importance and evolution of interconnects. Interconnect
capacitance and resistance .Local interconnects. RC delay of global
interconnects. Advanced interconnects - copper, low k dielectrics,
|End Line Characterisation
and parameter extraction
|| MOSFET testing - Threshold
voltage; Ion, Ioff testing; Effective channel length; Breakdown. Isolation,
leakage, ESD, Latch-up. Lithography and interconnects. MOSFET parameter
of CMOS process / device / circuit design and simulation 1
session will be led by NEC Semiconductors
|Integration of CMOS process
/ device / circuit design and simulation 2
session will be led by NEC Semiconductors
|DRAM Architectures and
DRAM Processing Technology
session will be led by NEC Semiconductors
and mixed signal CMOS
sesson will be led by Wlfson Microelectronics
- 'The future of silicon devices & systems'
review of the latest research in device scaling, and its implications
for future 'System on Chip' technologies.
to Bipolar Transistors
principles. Bipolar transistor band diagram. Forward active, inverse
active, saturation, cut-off. Common emitter, common base, common collector.
Base current, collector current, emitter current. Components of base
current Evolution of bipolar technology.
Assumptions. Basic equations. Boundary conditions in emitter and base.
Base current derivation Collector current derivation. Current gain.
Bandgap narrowing. Minority carrier mobility. Bandgap narrowing and
minority carrier mobility models. Majority carrier mobility. Lifetime.
layer and collector sink. Isolation. Junction isolation. A linear
bipolar process. Extrinsic base. LOCOS for bipolar processes. Oxide
isolated bipolar process. Walled emitters. Requirements for high speed.
Deep trench isolation for bipolar processes. Single polysilicon bipolar
processes. Quasi self-aligned emitte. Fully self-aligned emitter:
outside spacer. Complementary bipolar processes. Double polysilicon
bipolar process. Polysilicon extrinsic base .Self-aligned emitter
concept. Self-aligned emitter in practice. Process sequence for double
poly process. Transistor layout
of Simple Theory
doping profiles. Gain variation with collector current. Recombination
in the emitter/base depletion region. Sources of recombination in
depletion region. Series resistance, Emitter resistance. High current
gain.Early effect Avalanche breakdown. Zener breakdown. Breakdown
in bipolar transistors. Common emitter and common base breakdown voltages
||Scaling bipolar transistors.
Gain in scaled transistors. Polycrystalline silicon. Polysilicon emitters.
Dopant segregation. Polysilicon emitter physics. Interfacial oxide
layer. Base current. Emitter resistance. Surface recombination velocity.
Interface engineering. Polysilicon emitter design options. Emitter
plug effect. In-situ doped polysilicon. Stored charge in polysilicon
charge. Cut-off frequency and forward transit time. Base delay time.
Emitter delay time. Collector/base depletion region delay time. Forward
transit time. Breakdown of the components of the forward transit time.
constant of SiGe. Critical thickness. Bandgap. Heterojunction formation.
Parasitic energy barriers. Collector current. Gain enhancement. Cut-off
frequency and forward transit time. Device design trade-offs .SiGe
HBTs with graded Ge profile. Polysilicon emitters for SiGe HBTs. Conduction
band barrier. SiGe technology issues. SiGe HBT with a low doped emitter.
Models of Bipolar Transistors
model. Full model: saturation. Gummel-Poon model in forward active
region. Gummel-Poon model in reverse active region. Gummel-Poon model
in saturation. Extensions to the basic Gummel-Poon model. Recombination
in the emitter/base depletion region. Base, emitter and collector
resistances .Collector/base, emitter/base and collector/substrate
capacitances. Diffusion capacitance. Small signal model. Hybrid p
model. Cut-off frequency. Components of cut-off frequency. Measuring
forward transit time. Transistor design for high fT
Studies of SiGe HBT Technologies
SiGe HBT processes
of merit. Maximum oscillation frequency. ECL and CML .Gate delay expressions.
Transistor parameter calculation. Case study: Si double poly bipolar
technology optimisation Case study: SiGe HBT technology optimisation.
structured set of tutorials will be presented that cover the design
of bipolar transistors. These tutorials will consolidate the material
in the lecture notes, act as an introduction to the post-course work
and, of course, prepare you for the examination.
- "Fundamentals of Modern Devices",
Y Taur, T K Ning, Eds. C Y Chang and S M Sze,ULSI Technology, McGraw-Hill.(1998)ISBN:
0-521-55959-6 (paper back) 0-521-55056-4 (hard back)
This is the main book being used for this module.
- "Semiconductor Devices Explained
using Active Simulation", T Mouthaan, John Wiley (1999) ISBN:
- "Deep-Submicron CMOS IC's",
H Veendrick, Kleuwer Academic (2000), ISBN: 9-044-00111-6
- "ULSI Technologies", C.Y Chang, S.M.
Sze, McGraw-Hill.(1996) ISBN: 0-071-14105-7
Conference Papers & Journals:
- Y. Thaur, D.A. Buchanan, W. Chen,
D.J. Frank, K.E. Ismail, S.-H. Lo, G.A. Sai-Halasz, R. G. Viswanathan,
H.-J. C. Wann, S. J. Wind and H.-S. Wong, "CMOS scaling into the nanometer
regime", Proceedings of the IEEE, Vol. 85, No 4, pp. 486-504 (1997).
- S. Asai and Y. Wada, "Technology
chalanges for integration near and bellow 0.1 micron", Proceedings
of the IEEE, Vol. 85, No 4, pp. 505-519 (1997).
NB: Details of module content, timetable
and lecturers may be subject to change