Advanced Silicon Processing & Manufacturing Techniques

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MODULE PROFILE

Module Number: 14

Title: Oxides for sub 100nm Technology

Delivered by: University of Liverpool

Module Credits: 15

Assessment Weightings:

  • Pre-residential work: 3
  • Post-residential work: 7
  • Examination: 10

Convenor:

  • Professor Steve Hall, University of Liverpool

Lecturers/Tutors:
Internal:

  • Professor Steve Hall
  • Dr Steve Taylor
  • Dr Octavian Buiu

External:

  • Dr Jian Zhang, Liverpool John Moores University
  • Prof Harold Gamble, Queen’s University Belfast
  • Prof Olof Engstrom, MC2, Chalmers University, Sweden

Industrial:

  • Dr Guido Groeseneken, IMEC, Leuven, Belgium
  • Dr Steve Hodgskiss, Philips, UK

Industrial Advisors:

  • Dr G.Groeseneken, IMEC , Leuven, Belgium
  • Dr. Max Lemme, AMO, Germany
  • Dr . Steve Hodgskiss, Philips, UK

Aims:

The aim of this module is to provide delegates with a description of the electronic properties of dielectrics and the impact of dielectrics on the properties of MOS and other semiconductor devices. It includes discussions of growth methods and kinetics, scaling, reliability and techniques for the study of insulating films as they impact on MOS and SOI devices. Awareness of critical issues for the future will be addressed also by speakers from academia and industry

Learning objectives:

On successful completion of this module delegates will have gained:

  • an appreciation of the fundamental mechanisms controlling the formation of oxides

  • an understanding of the measurement of thickness and such electrical properties as density of interface states

  • a knowledge of conduction properties and trapping effects within the film

  • a knowledge of ion migration and the relationship to degradation

  • an in depth appreciation of the relationship of dielectric physical and electrical properties to real integrated devices

  • an overview of future trends of gate oxides for devices including decananometer CMOS processes with high-K replacements for silicon dioxide

Assessment:

  • Pre-residential sessions: assignments 15 %
  • Post-residential sessions: assignments 35 %
  • Examination (supervised) 50 %

    Background to the Module:

There is an increasing realisation that, as the problems of photolithography below 0.1 micron are overcome, the next major obstacle to further reductions in minimum feature size will be the very thin oxides needed and the high current densities that usually flow through such dielectrics. In addition, thick oxides continue to be important with an emphasis on lower dielectric constant to reduce capacitive effects. Furthermore, there is considerable world-wide activity in seeking a dielectric with a permittivity, to replace SiO2 . This activity will be reviewed and appraised using the knowledge gained on the module.

Pre-Requisite Knowledge:

Knowledge of basic electrical principles is mportant along with an understanding of basic calculus up to and including second order differential equations. A background in silicon technology is also important. In particular the relationship between the various processes should be understood. This module has a strong overlap with other modules covering device and processing technologies.

Delivery & Assignments:

  • Pre-residential sessions:
    • Directed reading
    • Problem solving/exercises

    Residential week (35 hours contact time):

    • Lectures
    • Demonstrations
    • Tutorials/case studies
    • Exercises

    Post- residential sessions:

    • Advanced tutorial questions/case studies
    • Written report (2000 - 4000 words)
    • Supervised examination

    (3 questions out of 5, 2 hours)

SYLLABUS

  • Lectures: 19 hours
  • Laboratory demonstrations 16 hours and other supervised work
Hours
Topic Content
2
MOS
Fundamentals
Gate oxide technology in context of scaled CMOS: technology, device and circuit aspects
2
Oxide Growth Deal Grove and Wolters Models, fabrication techniques, RTO, UV assisted etc, oxidation of SiGe, poly-Si etc, wafer cleaning , TCAD models
3
Oxide Properties
and MOS theory
Capacitance, losses, traps, intrinsic conduction and leakage mechanisms, optical properties CV plots: accumulation, depletion and inversionHigh and low frequency response and pulsed MOS, influence of fast and slow traps, effects of ionic contamination
4
Metrology Ellipsometry, alpha step, interferometry, etch rates, densification, anneal Electrical techniques: Extraction of fundamental parameters and parasitic charges from CV, IV and charge pumping, pulsed MOS
2
Degradation/
breakdown
Trapping effects, high fields and hot electrons, reliability. Breakdown models and statistics, constant voltage and current oxide stress, charge to breakdown
2
Plasma processing induced damage RF, Microwave, Inductively/capacitively coupled plasmas and charging model, Latent defect generation and practical examples, Effects of processing parameters, wafer level issues nd protection methods
3
Oxides for
applications
Gate oxides for power devices, memories, high performance; thick oxides for isolation, silicon-on-insulator (SOI)
3
Advanced topics Ultra thin oxides: issues of leakage, poly-depletion, quantum effects etc; nitrided oxides, high-K dielectrics: issues and contenders, multi-stack dielectrics

Recommended Texts

  • Silicon Processing for the VLSI Era, Vol 1 - Process Technology - Second Edition, S Wolfe, R W Tauber, Lattice Press ISBN 0-961-672- 161 (2000). [This is the main book for this Masters course and is available from the IGDS Office, University of Surrey at 90 inclusive of post and packing]

  • Semiconductor Material and Device Characterisation 2nd Ed.,DK Schroder, Wiley, ISBN 0-471-24139-3 (1998)

Conference & Journal Papers

  • J H Stathis, 'Reliability limits for the gate insulator in CMOS technology,' IBM J. Res. & Dev., Vol.46, No.2/3, pp. 265-285, March/May 2002]

  • E W A Young, 'The high-K challenges in CMOS advanced gate dielectric process integration,' ECS Proc. Vol. 2002-2, pp.735-746 (2002)

  • T Skotnicki and F. Boeuf, 'CMOS technology roadmap - approaching uphill specials,' ECS Proc. Vol. 2002-2, pp.720-734 (2002)

  • C M Osburn, 'Vertically scaled MOSFET gate stacks and junctions: how far are we likely to go?' IBM J. Res. & Dev., Vol.46, No.2/3, pp.299-315, March/May 2002

  • G. Groeseneken, R. Bellens, G. Van den bosch, and H. E. Maes, 'Hot-carrier degradation in submicrometer MOSFETs: from uniform injection towards the real operating conditions' Semiconductor Science and Technology, Vol.10, pp.1208-1220, (1995).

'State of the art' review papers from top international conferences will be given to delegates at the start of the module

TIMETABLE

NB: Details of module content, timetable and lecturers may be subject to change

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Module 14

 

   
Time
Monday
Tuesday
Wednesday
Thursday
Friday
09.00 - 10.30
Introduction, context and overview

 

Electronic Properties (I)
Advanced Characterisation Techniques
Steve Hodgskiss
(Philips)
Ultra-thin Oxides, Issues and Metrology
10.30 - 11.00
COFFEE
COFFEE
COFFEE
COFFEE
COFFEE
11.00 - 12.30
Growth Techniques and Oxide Properties
Electronic Properties (II)
Degradation
Guido Groeseneken (IMEC)
High-K
Dielectrics
12.30 - 14.00
LUNCH
LUNCH
LUNCH
LUNCH
LUNCH
14.00 - 15.30
TCAD Models for Oxide Growth
Laboratory Demonstration of Assessment
Plasma Induced Damage
Guido Groeseneken (IMEC)
Description of Post Residential Studies
15.30 - 16.00
TEA
TEA
TEA
TEA
TEA
16.00 - 17.30
Physical Properties and Metrology of Oxides
Metrology using C-V, I-V
SOI

Max Lemme
(AMO)


End of Course
19.00
 
COURSE BANQUET
Enquiries and further information from:

Mrs Sandra Peace
IGDS Programme Co-ordinator
IGDS Office
School of Electronics & Physical Sciences
University of Surrey
Guildford
Surrey
GU2 7XH UK

Tel +44 (0)1483 686 138
Fax +44 (0)1483 686 139
e-mail: s.peace@surrey.ac.uk
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