Advanced Silicon Processing & Manufacturing Techniques

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Module Number: 1.

Title: Introduction to IC Technology

Delivered by: University of Edinburgh

Module Credits: 15

Assessment Weighting:

  • Pre-residential work: 3
  • Post-residential work: 7
  • Examination: 10


  • Dr Les Haworth, University of Edinburgh


  • Dr Gerard Allan
  • Dr Rebecca Cheung
  • Mr Alan Gundlach
  • Dr Les Haworth
  • Dr Tony Snell
  • Dr Tom Stevenson
  • Dr Jonathan Terry
  • Professor Anthony Walton


  • Dr Alton Horsfall, University of Newcastle
  • Dr Nick Wright, University of Newcastle


  • Dr Dave Chivers, Ion Beam Services, Bathgate
  • Dr Mike Duncan, Motorola, East Kilbride
  • Dr Ian Underwood, MED Ltd.,

Industrial Advisors:

  • Dr David Wilson, Motorola, East Kilbride.
  • Dr Godfrey Gaston, Analog Devcies, Belfast


The aim of this module is twofold:
(i) to present the background science and technology of silicon IC processing and manufacture.
(ii) to enumerate and quantify the dependences of device/circuit performance upon the various process steps and technologies.

Learning Objectives:

On successful completion of this module delegates will have:

  • knowledge of silicon processing for existing and future technologies.
  • sound appreciation of the strengths and weaknesses of the competing technologies.
  • knowledge of the sensitivity of device performance upon processing parameters.
  • knowledge of the economics and drivers for new technologies.
  • appreciation of the importance of the SIA road map.
  • awareness of the strategies for integration of new processes in a manufacturing environment.


  • Pre-residential sessions: assignments 15 %
  • Post-residential sessions: assignments 35 %
  • Examination (supervised) 50 %

Background to the Module:

This module will provide a valuable overview of the processes and enabling technologies and the impact that these have upon circuit performance and thus is essential for those working in silicon manufacture.
The module is an essential component of this postgraduate programme and highlights the integration of the topics covered in other modules into a silicon whole process.

Pre-Requisite Knowledge:

This module is normally obligatory for all delegates who are expected at the outset to have a level of knowledge equivalent to a good honours graduate in a science or engineering discipline. However, delegates are not expected to have knowledge of all aspects of silicon processing, but it will be a major advantage to have had some exposure to one or two areas, which will enable delegates to contribute their own experience in those areas, creating a more interactive environment to the module.

Delivery & Assignments:

  • Pre-residential sessions:
    Directed reading
    Suggested booklist:
    • Silicon Processing for the VLSI Era, Vol: 1 - Process Technology - 2nd edition(2000), S Wolf & R W Tauber, Lattice Press, ISBN 0-961-672-161 (This is the main book used for this module and for the programme as a whole, it may be obtained from the IGDS Office)
    • Silicon Processing for the VLSI Era, Vol: 2 - Process Integration, S Wolf & R W Tauber, Lattice Press, ISBN 0- 9616721-4-5
    • Physics of Semiconductor Devices, 2nd Edition, S.M. Sze, Wiley, ISBN 0-471-09837-X
    • Microelectronic Devices, E.S. Yang, McGraw Hill, ISBN 0-07-072238-2
    • ULSI Technology, C Y Chang & S M Sze, McGraw Hill, ISBN 0-07-114105-7
    • Electronic Materials Science: for Integrated Circuits in Si and GaAs, J. W. Mayer and S. S. Lau, Macmillan, ISBN 0-02-378140-8.
    • The Science and Engineering of Microelectronic Fabrication, S. A. Campbell, Oxford University Press, ISBN 0-19-510508-7.
    • Intuitive IC Electronics, 2nd Edition, McGraw Hill, ISBN 0-07-021969-9.


    Written exercise: A report of 2500 - 3000 words based on reading from the above booklist, e.g. summarising why silicon has become the dominant semiconductor material. Include tables, figures and bullet lists, as appropriate.

  • Residential week (35 hours contact time):
    • Lectures
    • Laboratories/Simulation exercises
    • Case Studies
  • Post-residential sessions:
    • Tutorial questions/exercises
    • Technical report (3000-6000 words), e.g. describe metrology techniques used in manufacturing to measure oxide thickness, critical dimensions (CD) and doping impurity profiles.
    • Supervised examination (3 questions out of 5, 2 hours)



Lectures - 25 hours
Laboratory sessions - 8 hours
Case Study - 2 hours

Topic Content
Device Structures and Architectures: Material properties - conductors, semiconductors and dielectrics, parameters - mobility, resistivity etc, principle of operation.
MOS Integration and Devices: Standard MOS process flows and device/circuit performance, overcoming short-channel effects, integrating ultra-thin gate dielectrics and advanced gate stacks, low-k dielectrics, advanced metalisation.
Bipolar Integration: Common bipolar process flows, relating device. structures to circuit performance, advanced bipolar processes, HBTs, SiGe technology
BiCMOS and Power Device Integration: BiCMOS processes and integration, basic power structures (MOS and Bipolar), power IC technology.
TCAD Exercise (MOS Integration): Simulation exercise to explore the relationship between the implant and diffusion parameters, and gate oxide thickness and their effect on threshold voltage.
Memory Integration: Trench and stack DRAM, DRAM chip architectures, non-volatile memory, FLASH, EEPROM, smartcard technologies.
TCAD Exercise (Bipolar Integration): Simulation exercise to explore the transistor base region, highlighting the emitter push effect.
Scaling: SIA Roadmap, MOSFET miniaturisation, deep submicron, reduced power, increased speed, ultrathin oxides, ultrashallow junctions
Yield: Critical area, defects, faults, yield models, IC layout
Contamination: Particulates, yield formula, filtration of gases & liquids, de-ionised water, ionic contamination, C/V monitoring.
End of Line Characterisation and Parameter Extraction: Mobility, velocity saturation, threshold voltage, subthreshold, transconductance, channel length, series resistance, doping profiles, C-V
Reliability and Failure Mechanisms: Hot carriers, impact ionisation, substrate current, threshold drift, junction breakdown, contact failure, electromigration
Packaging and Assembly: Package types, die attachment, wire bonding, tab bonding, flip chip, multichip modules, package materials, package reliability
Lithography: SIA Roadmap, lithography requirements, CD and overlay, photoresist materials, optical and chemical properties, evolution of exposure equipment, contact/proximity/projection, wafer steppers - performance characterisation - process window - optimisation of exposure and focus, inspection and metrology for CD and overlay, limits of optical lithography, future trends
Etch: Etch chemistries, wet etch advantages & limitations, dry etch advantages & limitations, anisotropy, endpoint detection, selectivity
Implantation and Diffusion: Principles -distribution profiles, Fick's Law, defects range data; technology, yield/quality control, device implications - junction depth, sheet resistance, threshold voltage, electrical breakdown; 2nd Order Effects - crowding, channelling masking
Interactive Simulation (Implantation and Diffusion): Exercise to explore the relationship between implant energy and dose, and diffusion time and temperature on junction depth and sheet resistance.
Layer Growth: Thermal oxidation - Deal Grove Law, wet oxidation, dry oxidation, oxidation equipment, thin oxide growth, CVD - principle, chemistries, APCVD, LPCVD, PECVD, CVD equipment, epitaxy
TCAD Exercise (parameter extraction): Simulation of devices and extraction of SPICE model parameters
Interconnect: Interconnect metallurgy, diffusion barriers/silicides, evaporation, sputtering, technology issues, multi-layer metallisation, damascene, interconnect delay
The Future: Deep submicron, bulk CMOS, silicon on insulator, complexity-speed-power, nanodevices, single electron devices

Recommended Texts:

  • S Wolf, R W Tauber "Silicon Processing for the VLSI Era", Vol 1 - Process Technology, Lattice Press (1999), ISBN 0-961-672-161.NB: This is the main book for the module and should be ordered well in advance as it is sometimes a long delivery.
  • S Wolf, R W Tauber "Silicon Processing for the VLSI Era", Vol 2 - Process Integration, Lattice Press (1990), ISBN 0-9616721-4-5.
  • S.M. Sze Physics of Semiconductor Devices, 2nd Edition, Wiley, (1981), ISBN 0-471-09837-X.
  • S.M. Sze VLSI Technology, 2nd Edition, McGraw Hill, ISBN 0-07-100347-9.
  • Stephen A Campbell "The Science and Engineering of Microelectronic Fabrication", Oxford University Press (1996), ISBN 0-19-510508-7

Conference & Journal Papers

  • "Scaling the Gate Dielectric Materials, Integration and Reliabiltiy" Buchanan D A, IBM J. Res. Dev.43: (3), pp 245-264 (1999).
  • "Review of low-voltage CMOS LSI technology as a standard in the 21st century" Mutoh S, Solid State Electronics, 42: (5), ppA5-A16 (1998).
  • "Is there LOCOS after LOCOS ?, Deleonibus S, Solid State Electronics, 41: (7), pp1027-1039, (1997).
  • "CMOS scaling into the nanometer regime." Taur Y, Buchanan D A, Chen W, Frank D J, Ismail K E, Lo S H, SaiHalasz G A, Viswanathan R G, Wann H J C, Wind S J, Wong H S, Proc. IEEE, 85: (4), pp486-504, (1997).
  • "0.1 Ám complementary metal -oxide-semiconductors and beyond" Toriumi A, J. Vac. Sci. Technol. B, 14: (6), pp4020-4023, (1996).
  • "Reliability challenges for low voltage low power integrated circuits", Qual. Rel. Eng. Int., 12: (4), pp271-279, (1996).


NB: Details of Module content, timetable and lecturers, may be subject to change.

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Module 1


09.00 - 10.00
Bipolar Integration 2
Lithography 1
Interactive Simulation Implantation
10.00 - 11.00
Scaling - Device Structures and Architectures
BiCMOS and Power Device Integration
Lithography 2
Interactive Simulation Diffusion/Oxidation
11.00 - 11.15
11.15 - 12.15
MOS Integration and Devices 1
TCAD Exercise (Bipolar Devices)

Layer Growth 2(Oxidation + CVD)

12.15 - 13.00
13.00 - 14.00
MOS Integration and Devices 2
TCAD Exercise (Bipolar Devices)
EOL Characterisation and Parameter Extraction
Case Study
Later Growth 3
14.00 - 15.00
Bipolar Integration1
Memory Integration
Case Study
Interconnect 1
15.00 - 15.15
15.15 - 16.15
TCAD Exercise (MOS Devices)
Reliability/Failure Mechanisms
TCAD Exercise Parameter Extraction
Layer Growth 1 (Oxidation)
Interconnect 2
16.15 - 17.15
Packaging and Assembly
The Future (Course Ends)
Enquiries and further information from:

Mrs Sandra Peace
IGDS Programme
IGDS Office
School of Electronics & Physical Sciences
University of Surrey

Tel +44 (0)1483 686138
Fax +44 (0)1483 686139
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